1. Technical Field
This disclosure relates generally to integrated circuits and, more particularly to integration of chip-scale packaging input-output bump-connection metallurgy into integrated circuit structures.
2. Description of Related Art
Semiconductor integrated circuits (“IC”) in the state of the art have been able to pack millions of circuit elements into a relatively small die, or “chip”, e.g., having lateral area footprint, e.g., a ¼″ by ¼″. Most ICs are designed with input-output (“I/O”) pads located along the periphery of the chip; some requiring hundreds of such pads. These pads are then wire-bonded to connect the IC to the macro-world of a printed wire board (“PWB”), also known as printed circuit board (“PCB”), and surrounding discrete elements and other IC electronics on the board. This conventional perimeter-lead surface mount technology (“SMT”) for complex circuitry with appropriate interconnects often requires a chip carrier several times greater in size than the chip itself.
For mobile appliances—e.g., cellular telecommunications products, portable digital assistants (“PDA”), notebook computers, and the like—or applications where physical space for computers and instrumentations is extremely valuable—e.g., aircraft, space shuttles, and the like—individual component size and weight are factors which are critical to successful design. Thus, there is a conflict between a higher density of IC elements on the chip with attendant higher input/output (“I/O”) needs and a simultaneous demands for continuing miniaturization with increased functionality.
Wafer-level packaging (“WLP”), wherein a single IC die and its mounting package are manufactured and tested on a multi-die wafer produced by the IC manufacturer prior to singulation into individual chips, offers many advantages to the chip manufacturer. One WLP solution known in the art is generally referred to in the art as chip-scale packages (“CSP”). Chip-scale packaging technology, where the peripheral pad configuration is redistributed, provides die-sized packaging, allowing more condensed PCB patterns, also referred to in the art as “land patterns” where elements have a specific area “footprint.”
Exemplary, conventional, chip-scale technology is demonstrated by FIG. 1A and 1B, taken from Semiconductor International magazine, Oct. 2000, pp. 119-128, “Wafer-Level Packaging Has Arrived,” by Dr. Philip Garrou, illustrating the process 100, FIG. 1A, and resultant structure 102, FIG. 1B, for chip-scale packaging I/O redistribution. As shown in FIG. 1A, IC 101 peripheral I/O pads 103 are redistributed to bumps 107 via known manner processes, including a “Metallization” step 105 from pads 103. The process continues to an I/O bump formation step wherein the bumps 107 are located inwardly from the chip periphery. Conductive material (such as a metal, e.g., copper) beams 109 are lithographically defined superjacent the chip passivation layer 111 (e.g., a plasma nitride or the like) and within a protective-covering-stress-absorbing material (e.g., resin, polyimide, or the like) 113, providing a conventional wisdom IC, “Silicon,” with chip-scale packaging structure as shown in FIG. 1B. A variety of implementations are described by Garrou. In current wafer-level packaging, these additional layers of the chip-scale package are generally are so formed on the wafer after the die fabrication is completed, yielding a plurality of packaged die on the wafer, which has many advantages for the manufacturer. A thereafter singulated die with chip-scale package 115 with eight bumps 107 is illustrated in FIG. 1C, showing that the total footprint is essentially the same as the die area. The present invention relates to further discoveries in this regard.
Many publications describe the details of common techniques used in the fabrication of integrated circuits that can be generally employed in the fabrication of complex, three-dimensional, IC structures; see e.g., Silicon Processes, Vol. 1-3, copyright 1995, Lattice Press, Lattice Semiconductor Corporation (assignee herein), Hillsboro, Oreg. Moreover, the individual steps of such a process can be performed using commercially available IC fabrication machines. The use of such machines and common fabrication step techniques will be referred to hereinafter as simply: “in a known manner.” As specifically helpful to an understanding of the present invention, approximate technical data are disclosed herein based upon current technology; future developments in this art may call for appropriate adjustments as would be apparent to one skilled in the art.